The present invention relates to a semiconductor integrated circuit device. More specifically, the invention relates to technology that can be effectively adapted to a semiconductor integrated circuit device in which a wiring is connected to the source region or the drain region of a MISFET via a silicon film.
The semiconductor integrated circuit device having DRAM (dynamic random access memory) which is now being developed by the present inventors has memory cells each being constituted by a memory cell select MISFET and a capacitor element for storing data. The memory cell select MISFET of the memory cell is constituted by an n-channel of the LDD (lightly doped drain) structure. The capacitor element for storing data has a so-called planar structure in which a dielectric film and a plate electrode (upper electrode) are stacked in this order on the main surface of an n-type semiconductor region (lower electrode). The memory cell consists of a series circuit in which one semiconductor region of the memory cell select MISFET is connected to the lower electrode of the capacitor element for storing data.
The other semiconductor region of the memory cell select MISFET in the memory cell is connected to a data line via an intermediate electrically conductive film.
The data line is chiefly composed of aluminum having small resistance in order to increase the speed of operation for writing data onto the DRAM and to increase the speed of operation for reading the data.
The intermediate electrically conductive film is composed of a polycrystalline silicon film, and is connected to the other semiconductor region of the memory cell select MISFET in a region specified by a side wall spacer that is formed on the side wall of the gate electrode of the memory cell select MISFET. The side wall spacer is formed on the side wall of the gate electrode in a self-aligned manner. Therefore, the region specified by the side wall spacer is self-aligned with respect to the gate electrode. That is, the position where the intermediate electrically conductive film and the other semiconductor region are connected together is self-aligned with respect to the gate electrode of the memory cell select MISFET. An end of the intermediate electrically conductive film is drawn onto the gate electrode of the memory cell select MISFET. That is, the intermediate electrically conductive film is so constituted as can be reliably connected to the data line even in case the masking is deviated in the step of fabrication. The intermediate electrically conductive film and the gate electrode are electrically isolated from each other.
The intermediate electrically conductive film is formed by a method described below.
First, one and the other semiconductor regions (source region and drain region) of a memory cell select MISFET are formed.
Then, a side wall spacer is formed on the side wall of a gate electrode of the memory cell select MISFET. In this step or in the next step, a connection hole is formed on the other semiconductor region of the memory cell select MISFET within a region specified by the side wall spacer.
Next, a polycrystalline silicon film is deposited so as to come into contact with the other semiconductor region through the connection hole. The polycrystalline silicon film does not contain impurities for controlling the resistance or contains impurities at a low concentration.
N-type impurities (P or As ions) are introduced at a high concentration into the polycrystalline silicon film followed by the heat treatment so that the polycrystalline silicon film possesses a predetermined small resistance.
The polycrystalline silicon film is patterned into a predetermined shape thereby to form an intermediate electrically conductive film.
Then, an interlayer insulating film is formed on the intermediate electrically conductive film, and a connection hole is formed in the interlayer insulating film on the intermediate electrically conductive film. A data line is formed on the interlayer insulating film so as to come into contact with the surface of the intermediate electrically conductive film through the connection hole.
The intermediate electrically conductive film thus formed helps increases the masking margin in the step for forming the other semiconductor region of the memory cell select MISFET through up to the step for forming the data line. That is, there is no need of maintaining a masking margin between the connection hole and the other semiconductor region of the memory cell select MISFET, and the other semiconductor region of the memory cell select MISFET can be reduced. Therefore, the area occupied by the memory cell is reduced and the integration degree of the DRAM can be increased.
The DRAM which uses such an intermediate electrically conductive film has been described, for example, in U.S. Ser. No. 241,732 (filed Sept. 8, 1988).